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Beta Timing Setup and Data Processing at UZH

NOTE: This post was originally published in this link. Matías Senger(matias.senger@cern.ch)On behalf of the UZH group: Anna Macchiolo, Riccardo del Burgo, Daniel Hernandez, Yuta Takahashi, Prof. Ben Kilminster 37th RD50 WorkshopNovember 20, 2020 UZH beta timing setup The UZH beta timing setup has the following block diagram: Hardware elements of the setup Bias voltage: CAEN …

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