I am working in the development of a position+time readout chip for 4D pixel detectors in collaboration with the group at PSI. The project has already started when I joined and there are already some designs that have been implemented in test structures, which have to be characterized. For this, the group at PSI developed a test setup which is controlled by a Raspberry Pi and has an FPGA with some peripherals, you can see in the following pictures:
The setup is composed of many boards that interconnect between themselves. One of the boards, which is the core of the setup for TDCTime to Digital Converter. testing, contains two SY89296 delay chips that produce a start and a stop signals with a very precise time difference that can be controlled digitally. Below there is a picture of the so called “adapter board” with the two delay chips and the lines that carry the signal from the chips to the connector where later on the test structure will be.
This is very nice for characterizing the TDC test structures because we can program a specific time difference between the start and stop signal and see how the TDC responds. But before taking any conclusion from such a test of a TDC we must know how precise and accurate this test setup is. So today I will write about this.
The setup for this characterization is very simple, as you can see in this picture:
A block diagram of the setup can be sketched like this:
The FPGA produces a pair of pulses each for each input of the delay chips, labeled A and B. Each of these chips has some specific configuration for D and FTUNE. As a result, each produces a certain delay until the output transitions from 0 to 1. The two outputs are measured with the oscilloscopeLecroy WaveRunner 640Zi, 4 GHz, 40 GS/s..
I just connected each of the two outputs from the delay chips to the two inputs of a high speed oscilloscope and started measuring the time difference between each signal for different programming configurations. To measure the time difference between the two signals I used one of the “measure functions” provided by the oscilloscope. I configured it to measure the time difference between two rising edges at a level of 1 V, as seen in the following screenshot:
After setting up the oscilloscope I proceeded to program the Raspberry Pi (which is part of the PSI test setup) to scan on the delay difference between the two chips. If we look into the datasheet of these chips, they have two ways of controlling the delay:
- Through the digital value written to the
D[9:0]control bits. This is the main delay control and goes from 0 to 9 ns in steps of about 10 ps.
- Through the analog voltage in the
FTUNEpin. As the name suggests, this provides a fine tune of the delay. It goes from 0 to 50 ps with a voltage that ranges from 0 to 1.25 V.
Results of measurements
I proceeded to measure the delay as a function of each of these two settings, D and FTUNE, separately.
Delay vs D[9:0]
Let’s start with the delay measured for different values of D. For each value of D shown in this section I measured Δt for 999 events. So at each value of D I have 999 different Δt values. I studied each of the two delay chips individually. So when I was sweeping D for chip A I left D=0 in chip B and viceversa.
If I average all the Δt values at each D I obtain this:
As can be seen the chip A produces positive values of Δt while chip B produces negative values. Since D is supposed to be the delay in tens of picosecond I have plotted with the x axis being D×10 ps, and I have also plotted y = |x| which is what the delay ideally should follow. There are, however, a number of appreciable deviations from this ideal behavior.
- To start with, there is an offset. If you zoom into the region where D=0 you will note there is an offset of about 100 ps. There are many possible reasons for this offset: Internal offsets from the chips themselves, an offset from the two signals produced by the FPGA and even a difference in the length of the two cables I used to connect the oscilloscope (a difference in time of 100 ps should correspond to a difference in length of about 2 cm which is certainly possible).
- Another effect we can see is that the slope of each line is not what we would expect (compare against y = |x|). The reason for this can only be attributed to the delay chips.
- Finally, there is a “high frequency oscillation” that seems to be constant along all the two lines. If you zoom in in any region you will appreciate it better. This effect can only be attributed to the delay chips.
The previous plot shows an “absolute measurement of Δt”. In order to compare the behavior of each delay chip with the other I subtracted the offset from the two lines and inverted the one for chip B. This is what I got:
Here it is very clear that the slope is not exactly 10 ps/D and also that each chip has a slightly different slope. We can also see that the high frequency oscillations are exactly the same for the two delay chips.
In page 10 of the datasheet we find the specification for the delay in picoseconds vs the value of D. There we see that the slope is specified to be 9 ps/D. As far as I know it is not mentioned the high frequency oscillation and the variations of this slope from chip to chip.
Delay fluctuations vs D
Another important question is: How does Δt fluctuates? To address this question I just took the same dataset I showed before and observed the distribution and standard deviation of Δt at each value of D. The distribution of Δt looks very Gaussian, as can be appreciated in this example:
From this fit I obtain a fluctiation of 3.71 ps. Repeating this for all values of D I obtain this:
Here we see that there seems to be a slight increase in the fluctuations for higher values of D. The fluctuations of Δt are around 3.4-3.8 ps.
Delay vs FTUNE voltage
Next I proceeded to characterize Δt vs the FTUNE voltage. I proceeded the same way: When I was varying FTUNE for chip A I left FTUNE for chip B at 0 V. Also, the value of D for both chips was left constant at 0. This is what I obtained:
As we see, the behavior this time is inverted as chip B produces positive delays and chip A negative ones, while for D this was the opposite way around, and it is also nonlinear. These two aspects are expected from the specification in page 10 of the datasheet.
Removing the offset and plotting the two curves together we get:
Here we see that there is a slight difference between the two chips, too. This is expected from the datasheet.
Delay fluctuations vs FTUNE voltage
I also studied the fluctuations as the voltage in the FTUNE pin was varied. This is my result:
We se that there is no appreciable dependence and that the fluctuations are around 3.8 ps.
Using the information from the characterizations presented before I developed a program that automatically chooses the value for DA, DB, FTUNEA and FTUNEB in order to obtain some given delay. As can be seen in the next plot, the result was good.
With this program it is possible to choose a given value for Δt in seconds, either positive or negative, and the two chips are configured using the calibration measurements to produce such Δt.
When testing this calibration I noticed that this setup seems to be very sensitive to temperature variations. To expose this I have measured many times the obtained delay given a certain set delay for different conditions, but always using the same calibration. Between each of these measurements I changed the warm-up-time before the measurement, just a dead time with the chips on before starting to measure, and also the measurement speed by changing the number of samples of Δt I took for each set time (the more samples the less the speed but higher statistics). When plotting the error in the obtained average delay with respect to the set delay, i.e. “average measured delay minus set delay” I obtain this:
First let’s start comparing all the curves at speed 2.474 (this speed is arbitrary, I defined taking into account the number of samples taken at each set delay and the number of different values of set delay measured). It is possible to hide the other curves by clicking on the legend of the plot. For these curves we see that the best ones are those two with 5 minutes warm up, because they have the smallest delay error. The other two curves, “no warm up” and “1 min warm up” have a very big error at -4 ns, which is where the measurement started. For higher values of set delay the error is less, this is because as the time passed the chips warmed up. Between these two measurements we see that the measurement with no warm up is better than the measurement with 1 minute warm up. I don’t understand this, I have some ideas but with no certainty to understand these result.
Now we can compare the two curves with no warm up but with different speeds. We see that the one that has speed 0.243 is better than the other one. This is reasonable if the effect is due to warm up because a the two measurements took the same time to warm up but one of them is slower, so it takes more samples after it has already warmed up.
Finally, we can look at the “high statistics, speed 0.008” trace. This measurement was taken during a long time laps (about 15 hours in total). In this measurement we can see some interesting effects. First, between -4 ns and -3.9 ns we see that there seems the be a similar effect of warm up as in the previous measurements discussed. Next, the delay error slowly increases at a constant rate. Between 3.5 ns and 3.65 ns there is a strange peak and then the curve continues until in the end starts to decrease. The peak at 3.5 ns concides with the moment a person opened the door of the lab and entered there for a few minutes, so my suspect is that there was some change in the temperature of the room due to opening the door and this produced this peak. The slow positive slope along the whole trace may be an effect of the daily temperature modulation.
With respect to the fluctuations in the delay, I obtained this for each of the previous measurements:
As can be seen the measurements with no warm up and the one with 1 min warm up start at -4 ns with a high fluctuation. This is consistent with a warm up transient period. Some of the traces have peaks at other times. Since these measurements have low statistics (33 samples at each value of set delay, except the “high statistics” trace which has 999 samples at each point) these peaks are probably statistical fluctuations and we can ignore them. In average, the fluctuations were between 4 and 4.5 ps, as seen. There is also an effect I cannot understand yet that the fluctuations seem to slightly increase, up to 6 ps, to the end of the measurements (set delay = 4 ns). In the high statistics trace we can also see a small modulation, which I don’t understand.
To conclude with the calibration, we can compare the results before and after this calibration was implemented. Just for ease of comparison, I will put again two of the plots previously shown:
Despite all the effects observed, we can see that this calibration greatly improves the results.
During the process I developed a Python package with the aim to easily control the PSI test setup using a modern programming language. The software can be found in this linkAs of now, the latest commit is 930da4eabf375a8d2da5784a833483c64fc59429.. The package can be easily installed in the Raspberri Pi of the test setup with a single command and then imported into any Python program. For more details see the
Readme.md file in the repository.
- The timing characteristics of the test setup were studied.
- The fluctuations in the Δt between the start and the stop signals, that will command the TDC, were found to be between 3.5 and 4.5 ps no matter which is the set delay.
- A number of deviations from the specified behavior in the datasheet of the delay chips were found. Most of them could be corrected after a calibration procedure was implemented.
- An important dependence between the mean value of the delay and the duration of the warm-up-period was found, probably due to the temperature increase of the delay chips.
- There are some deviations that were observed and are still not understood.
|↑1||Time to Digital Converter.|
|↑2||Lecroy WaveRunner 640Zi, 4 GHz, 40 GS/s.|
|↑3||As of now, the latest commit is 930da4eabf375a8d2da5784a833483c64fc59429.|